1. Field of the Invention
The present invention relates to test circuits for DC testing and methods for DC testing using the same. The invention particularly relates to a test circuit for DC testing which has a simple layout design and never causes malfunction due to simultaneous change of signals, and a method of DC testing using the same.
2. Description of the Background Art
In manufacturing an LSI (Large Scale Integration), DC (Direct Current) characteristics of output allowable buffers are generally measured as a manufacturing test. The output allowable buffers include an output buffers, a tristate buffer, a bidirectional buffer or the like. In DC testing, the output allowable buffers must be tested when L (Low) potential is output and also when H (High) potential is output. Thus, in DC testing, the output allowable buffers must assume, at least once, a state in which all of its outputs are low and a state in which all of its outputs are high, respectively.
Conventionally, DC testing is performed using a function pattern for verifying the function of an LSI which is prepared by an LSI designer.
Referring to FIG. 1, a conventional DC test unit for output buffers includes: a function pattern storage 1 for storing a function pattern prepared by a designer; a measuring period analysis unit 2 connected to function pattern storage 1 and analyzing periods at which a plurality of output allowable buffers must be DC tested based on the function pattern; a measuring period storage 3 connected to measuring period analysis unit 2 and storing analysis result from measuring period analysis unit 2; a pattern supply unit 4 connected to function pattern storage 1 and measuring period storage 3, and supplying the function pattern for an LSI under measurement in accordance with the measuring period; a mounting portion for the LSI under measurement 6 mounting the LSI under measurement and receiving the pattern from pattern supply unit 4; and a DC measurement unit 5 connected to measuring period storage 3 and performing DC testing of an LSI under measurement mounted to mounting portion for the LSI under measurement 6 for each measuring period.
The function pattern prepared by the designer for LSI verification is stored in function pattern storage 1. Function pattern storage 1 is implemented in the form of storage such as an HDD (Hard Disk Drive).
Measuring period analysis unit 2 receives the function pattern from function pattern storage 1 and extracts the periods during which L and H signals are output, respectively, for each of the plurality of output allowable buffers. Generally, each output allowable buffer has a plurality of periods during which L or H signals are output. A minimized measuring period is calculated based on the outputs of L and H signals from each output enable buffer, so that DC testing is efficiently performed. The measuring period, a name of the output allowable buffer which can be measured with the measuring period, and an output potential (an output value) of the output allowable buffer are stored in measuring period storage 3. Generally, the analysis is preliminary executed by a computer.
Pattern supply unit 4, DC measurement unit 5 and mounting portion for an LSI under measurement 6 are contained in a usual LSI tester.
DC testing of the LSI under measurement is performed based on the function pattern and the measuring period. Pattern supply unit 4 supplies the function pattern, which has been stored in function pattern storage 1, for the LSI under measurement mounted on mounting portion for an LSI under measurement 6. Pattern supply unit 4 stops the supply of the function pattern when the measuring period is attained, and DC measurement unit 5 performs DC testing of the output allowable buffer which can be measured.
The DC testing however suffers from the following disadvantages. The DC testing is performed using the function pattern prepared by the designer. Thus, such function pattern must be prepared such that the output allowable buffers can be brought into the states in which all of its outputs are at L and H, respectively. As a result, the function pattern cannot be quickly produced and tends to be large in size. In addition, as the number of output allowable buffers increases, it becomes more difficult to make all the outputs from the output allowable buffers L or H outputs simultaneously. As a result, the number of periods for DC testing increases, thereby reducing test efficiency.
To solve this problem, there exists a method of readily preparing the function pattern required for DC testing by adding a test circuit for DC testing to the LSI.
Referring to FIG. 2, the LSI having the test circuit for DC testing includes: a system logic 9 constituting a system; selectors 8a to 8d each selecting and outputting one of an output value from system logic 9 and a value of a DCtestDataIn signal line 11 in accordance with a value of a DCtestSelect signal line 10; and output buffers 7a to 7d respectively connected to the outputs from selectors 8a to 8d for outputting the output values from selectors 8a to 8d. It is noted that input buffers and those output buffers which are not subject to DC testing are not shown in FIG. 2 for clarity of the drawing. The test circuit can control the output values from output buffers 7a to 7d by setting the value of DCtestSelect signal line 10 such that each of selectors 8a to 8d outputs the value of DCtestDataIn signal line 11. Thus, the function pattern can readily be generated, minimizing the period for DC measuring.
In a method of DC testing using the LSI including the conventional test circuit for DC testing, however, all of the output values from output buffers 7a to 7d are simultaneously changed from L to H or H to L. Such simultaneous change of the outputs possibly causes malfunction of the LSI per se, thereby disadvantageously preventing stable DC testing.
One method of testing an integrated circuit is disclosed in Japanese Patent Laying-Open No. 6-300814 as solving the problem related to the simultaneous change of outputs. In the method, output allowable buffers are divided into several groups to prevent the simultaneous change of outputs, and each group is DC tested in a similar manner as described above. In dividing the output allowable buffers into several groups to prevent the simultaneous change of the outputs, power supply sources of the output allowable buffers included in one group must be selected as separately as possible. However, the output allowable buffers connected to the same power supply pin are generally close to each other in the space, so that the output allowable buffers connected to different power supply pins are mutually spaced apart. Thus, addition of a test circuit to the output allowable buffers which are divided into groups to prevent the simultaneous change of the outputs causes another problem, that is, difficulty in layout design associated with the lengthy distribution of wires in the LSI.